This invention relates to a semiconductor memory, and more particularly to a semiconductor integrated circuit memory.
As typified by a dynamic random access memory (DRAM) or a semiconductor memory using a charge coupled device (CCD memory), a semiconductor memory having a high integration density stores data by making the existence and absence of charge inside a potential well on a semiconductor surface correspond to digital signals "1" and "0".
However, this storing method involves the problem that in the case of DRAM, for example, only binary 1-digit (1-bit) data can be handled for each unit memory cell, and hence the amount of total bits per chip is limited.
Particularly in the charge storage type memory such as described above, charge leaks from a pn junction formed essentially in a charge storage portion so that the data can be stored only for a limited period of time. This results in another problem that a mechanism for rewriting (refreshing) the stored data on a certain cycle of time within that period is essentially necessary.
The CCD memory has a structure in which the stored charge is cycled using a transfer electrode. In order to effect rewrite (refresh), therefore, the stored charge is transferred along a CCD transfer electrode loop arranged cyclicly, and the charge must be read and written at an input-output portion disposed at a predetermined position inside the CCD loop on a certain cycle of time. However, a great deal of power is necessary to charge and discharge the transfer electrodes for transferring the charge in order to refresh all data, and it has therefore been difficult in the past to provide a memory having low power consumption.
Semiconductor memories having higher integration density as exemplified by a semiconductor dynamic random access memory (hereinafter called "DRAM") have been developed every year, and miniaturization of unit memory cells (hereinafter called "memory cells") of the semi-conductor memory and its peripheral circuits is ever-increasing. In order to improve the integration density by miniaturization such as described above, however, a drastic improvement must be made in device process techniques such as photolithography, etching and the like. Unfortunately, a considerably long period of time is generally necessary before improved device process techniques are developed.
In contrast, demands for very high integration density semiconductor memories are ever-increasing, and semiconductor memories having low power consumption are earnestly required in a novel field of application such as miniature computers for office use and their peripheral terminals that have made remarkable progress in recent years. For these reasons, existing semiconductors are not entirely satisfactory not only in their integration density but also in their performance charactertistics such as power consumption.
To fulfil the demands described above, semiconductor memories using multiple level storage structure (MLS memories) are believed to be effective means that can realize very high integration density semiconductor memories and are available in accordance with the existing process technique. The memory improves substantially the integration density by storing data of at least more than two levels per memory cell.
A multi-level storage memory using a charge coupled device (hereinafter called "CCD") has been known in the past. The memory is described in detail in L. Terman et al. IEEE Journal of Solid-State Circuits, Vol. sc-16, No. 5, pp. 472-478, Oct. 1981, and M. Yamada et al, Proceedings of the 9th Conference on Solid-State Devices, Tokyo, 1977, pp. 263-268, issued on Jan., 1978, for example.
However, the multi-level storage memory using the charge coupled devices (CCD) has not been put into much practical application for the following reasons.
(1) Since signal charge transfer inefficiency is not zero in CCD, analog signal charge corresponding to multi-level data damps with the charge transfer, and hence the number of multi-levels can not be increased very much.
(2) The amplitude of a driving pulse must be increased in order to improve the signal charge transfer efficiency, and this results in extremely great power consumption in addition to the inherent property of the cell that it has originally large capacitance load.
(3) Since A/D and D/A convertors having high accuracy are necessary for each CCD loop, the integration density can not be increased due to the limitation of peripheral circuits, even if the memory cell can be miniaturized.